A major consideration in the design of analog-to-digital converters (ADCs) is capacitor mismatch errors. Various calibration techniques to correct them have been developed in both analog and digital domains. Digital background calibration is one class of such techniques.
While a number of digital background calibration techniques are known or researched, there is a need for simpler, more effective, and more cost-efficient methods for calibrating out capacitor mismatch errors.
Correlation based digital background calibration is being widely studied as a means to mitigate component mismatch errors in pipelined ADCs. Currently, a pronounced drawback of the correlation-based digital background calibration is slow convergence. With reasonable calibration circuit cost, it typically takes several 10 T samples for the calibration to converge within 12-bit accuracy. A higher resolution requires even more samples.
There is a need for methods and systems that can accelerate convergence in correlation based digital background calibration, without sacrificing convergence accuracy.